A display panel has a substrate and pixel elements formed thereon. These pixel elements are substantially arranged in the form of a matrix having gate lines in rows and data lines in columns. The display panel is driven by a driving circuit including a gate driver and a source driver. The gate driver generates a plurality of gate signals (scanning signals) sequentially applied to the gate lines for sequentially turning on the pixel elements row-by-row. The source driver generates a plurality of data signals (source signals), i.e., sequentially sampling image signals, simultaneously applied to the data lines in conjunction with the gate signals applied to the gate lines for displaying an image on the panel.
FIG. 8 is a block diagram of a conventional source driver 10 of a display. The source driver 10 includes a shift register (not shown), a first latch array 11, a first multiplexer array 12, a second latch array 13, a level shifter array 14, a digital-to-analog converter (DAC) array 15, a second multiplexer array 16, and an output buffer array 17. The source driver 10 is electrically coupled to a data input processor (data register) 20 having a Mini-LVDS input interface 21 and a Series to Parallel converter 22.
Image signals, LV0, LV1, . . . , RV2, are first received in the Mini-LVDS 21 and processed into a digital image format appropriate to the spatial addressing and the gray scale capabilities of the display, i.e., pixel data signals, having R, G, B components corresponding red, green and blue color signals, respectively. Each color signal is composed of N bits. The pixel data signals are converted from a serial format to a parallel format in the Series to Parallel converter 22, and then outputted to the first latch array 11 via bus lines 23. The shift register sequentially outputs a plurality of enable signals to the first latch array 11. The first and second latch arrays 11 and 13 latch and output the pixel data signal in response to the enable signals. The first multiplexer array 12 having a plurality of MUXs is arranged between the first and second latch arrays 11 and 13 for determining a path of the pixel data signals output from the first latch array 11 to the second latch array 13 in response to a polarity control signal POL from a timing controller (not shown). The level shifter array 14 receives the pixel data signals from the second latch array 13, changes the voltage level of the pixel data signals and then outputs the pixel data signals to the DAC array 15. The DAC array 15 converts the pixel data signals received from the level shifter array 14 into analog pixel signals. The second multiplexer array 16 having a plurality of MUXs outputs the analog pixel signals received from the DAC array 15 to the output buffer array 17 selectively in paths according to the polarity control signal POL. Finally, the output buffer array 17 writes the analog pixel signals (i.e., the image signals) to the panel pixels, for example, liquid crystal cells, for display.
As shown in FIG. 9, the polarity control signal POL has a polarity inverted periodically. It is the periodic polarity inversion of the polarity control signal POL that enables the control of the polarities of the pixel data R, G, and B, through the first and second multiplexer arrays 12 and 16. However, the polarity inversion circuit including the first and second multiplexer arrays 12 and 16 may physically occupy about 3% or more of an area of the source driver on a display panel. The more bits the pixel data R, G and B, the more MUXs in the first and second multiplexer arrays 12 and 16, thereby increasing the complexity and manufacture cost of the source driver.
Therefore, a heretofore unaddressed need exists in the art to address the aforementioned deficiencies and inadequacies.